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Uedu Open / Computation Structures
6.004

Computation Structures

Prof. Steve Ward | Spring 2009
Data Science, Analytics & Computer Technology Software Design and Engineering Computer Science Science & Math Mathematics Engineering Electrical Engineering Computation
前往原始課程
CC BY-NC-SA 4.0
課程簡介

6.004 offers an introduction to the engineering of digital systems. Starting with MOS transistors, the course develops a series of building blocks — logic gates, combinational and sequential circuits, finite-state machines, computers and finally complete systems. Both hardware and software mechanisms are explored through a series of design examples.

6.004 is required material for any EECS undergraduate who wants to understand (and ultimately design) digital systems. A good grasp of the material is essential for later courses in digital design, computer architecture and systems. The problem sets and lab exercises are intended to give students “hands-on” experience in designing digital systems; each student completes a gate-level design for a reduced instruction set computer (RISC) processor during the semester.

Course Information
SourceMIT 開放式課程
科系Electrical Engineering and Computer Science
LanguageEnglish
影片數172
課程影片 (172)
1
1.2.1 What is Information?
1.2.1 What is Information?
2
1.2.2 Quantifying Information
1.2.2 Quantifying Information
3
1.2.3 Entropy
1.2.3 Entropy
4
1.2.4 Encoding
1.2.4 Encoding
5
1.2.5 Fixed-length Encodings
1.2.5 Fixed-length Encodings
6
1.2.6 Signed Integers: 2's complement
1.2.6 Signed Integers: 2's complement
7
1.2.7 Variable-length Encoding
1.2.7 Variable-length Encoding
8
1.2.8 Huffman's Algorithm
1.2.8 Huffman's Algorithm
9
1.2.9 Huffman Code
1.2.9 Huffman Code
10
1.2.10 Error Detection and Correction
1.2.10 Error Detection and Correction
11
1.2.11 Error Correction
1.2.11 Error Correction
12
1.2.12 Worked Examples: Quantifying Information
1.2.12 Worked Examples: Quantifying Information
13
1.2.12 Worked Examples: Two's Complement Representation
1.2.12 Worked Examples: Two's Complement Representation
14
1.2.12 Worked Examples: Two's Complement Addition
1.2.12 Worked Examples: Two's Complement Addition
15
1.2.12 Worked Examples: Huffman Encoding
1.2.12 Worked Examples: Huffman Encoding
16
1.2.12 Worked Examples: Error Correction
1.2.12 Worked Examples: Error Correction
17
2.2.1 Concrete Encoding of Information
2.2.1 Concrete Encoding of Information
18
2.2.2 Analog Signaling
2.2.2 Analog Signaling
19
2.2.3 Using Voltages Digitally
2.2.3 Using Voltages Digitally
20
2.2.4 Combinational Devices
2.2.4 Combinational Devices
21
2.2.5 Dealing with Noise
2.2.5 Dealing with Noise
22
2.2.6 Voltage Transfer Characteristic
2.2.6 Voltage Transfer Characteristic
23
2.2.7 VTC Example
2.2.7 VTC Example
24
2.2.8 Worked Examples: The Static Discipline
2.2.8 Worked Examples: The Static Discipline
25
3.2.1 MOSFET: Physical View
3.2.1 MOSFET: Physical View
26
3.2.2 MOSFET: Electrical View
3.2.2 MOSFET: Electrical View
27
3.2.3 CMOS Recipe
3.2.3 CMOS Recipe
28
3.2.4 Beyond Inverters
3.2.4 Beyond Inverters
29
3.2.5 CMOS Gates
3.2.5 CMOS Gates
30
3.2.6 CMOS Timing
3.2.6 CMOS Timing
31
3.2.7 Lenient Gates
3.2.7 Lenient Gates
32
3.2.8 Worked Examples: CMOS Functions
3.2.8 Worked Examples: CMOS Functions
33
3.2.8 Worked Examples: CMOS Logic Gates
3.2.8 Worked Examples: CMOS Logic Gates
34
4.2.1 Sum of Products
4.2.1 Sum of Products
35
4.2.2 Useful Logic Gates
4.2.2 Useful Logic Gates
36
4.2.3 Inverting Logic
4.2.3 Inverting Logic
37
4.2.4 Logic Simplification
4.2.4 Logic Simplification
38
4.2.5 Karnaugh Maps
4.2.5 Karnaugh Maps
39
4.2.6 Multiplexers
4.2.6 Multiplexers
40
4.2.7 Read-only Memories
4.2.7 Read-only Memories
41
4.2.8 Worked Examples: Truth Tables
4.2.8 Worked Examples: Truth Tables
42
4.2.8 Worked Examples: Gates and Boolean Logic
4.2.8 Worked Examples: Gates and Boolean Logic
43
4.2.8 Worked Examples: Combinational Logic Timing
4.2.8 Worked Examples: Combinational Logic Timing
44
4.2.8 Worked Examples: Karnaugh Maps
4.2.8 Worked Examples: Karnaugh Maps
45
5.2.1 Digital State
5.2.1 Digital State
46
5.2.2 D Latch
5.2.2 D Latch
47
5.2.3 D Register
5.2.3 D Register
48
5.2.4 D Register Timing
5.2.4 D Register Timing
49
5.2.5 Sequential Circuit Timing
5.2.5 Sequential Circuit Timing
50
5.2.6 Timing Example
5.2.6 Timing Example
51
5.2.7 Worked Example 1
5.2.7 Worked Example 1
52
5.2.8 Worked Example 2
5.2.8 Worked Example 2
53
6.2.1 Finite State Machines
6.2.1 Finite State Machines
54
6.2.2 State Transition Diagrams
6.2.2 State Transition Diagrams
55
6.2.3 FSM States
6.2.3 FSM States
56
6.2.4 Roboant Example
6.2.4 Roboant Example
57
6.2.5 Equivalent States; Implementation
6.2.5 Equivalent States; Implementation
58
6.2.6 Synchronization and Metastability
6.2.6 Synchronization and Metastability
59
6.2.7 Worked Examples: FSM States and Transitions
6.2.7 Worked Examples: FSM States and Transitions
60
6.2.7 Worked Examples: FSM Implementation
6.2.7 Worked Examples: FSM Implementation
61
7.2.1 Latency and Throughput
7.2.1 Latency and Throughput
62
7.2.2 Pipelined Circuits
7.2.2 Pipelined Circuits
63
7.2.3 Pipelining Methodology
7.2.3 Pipelining Methodology
64
7.2.4 Circuit Interleaving
7.2.4 Circuit Interleaving
65
7.2.5 Self-timed Circuits
7.2.5 Self-timed Circuits
66
7.2.6 Control Structures
7.2.6 Control Structures
67
7.2.7 Worked Examples: Pipelining
7.2.7 Worked Examples: Pipelining
68
7.2.7 Worked Examples: Pipelining 2
7.2.7 Worked Examples: Pipelining 2
69
8.2.1 Power Dissipation
8.2.1 Power Dissipation
70
8.2.2 Carry-select Adders
8.2.2 Carry-select Adders
71
8.2.3 Carry-lookahead Adders
8.2.3 Carry-lookahead Adders
72
8.2.4 Binary Multiplication
8.2.4 Binary Multiplication
73
8.2.5 Multiplier Tradeoffs
8.2.5 Multiplier Tradeoffs
74
8.2.6 Part 1 Wrap-up
8.2.6 Part 1 Wrap-up
75
9.2.1 Datapaths and FSMs
9.2.1 Datapaths and FSMs
76
9.2.2 Programmable Datapaths
9.2.2 Programmable Datapaths
77
9.2.3 The von Neumann Model
9.2.3 The von Neumann Model
78
9.2.4 Storage
9.2.4 Storage
79
9.2.5 ALU Instructions
9.2.5 ALU Instructions
80
9.2.6 Constant Operands
9.2.6 Constant Operands
81
9.2.7 Memory Access
9.2.7 Memory Access
82
9.2.8 Branches
9.2.8 Branches
83
9.2.9 Jumps
9.2.9 Jumps
84
9.2.10 Worked Examples: Programmable Architectures
9.2.10 Worked Examples: Programmable Architectures
85
10.2.1 Intro to Assembly Language
10.2.1 Intro to Assembly Language
86
10.2.2 Symbols and Labels
10.2.2 Symbols and Labels
87
10.2.3 Instruction Macros
10.2.3 Instruction Macros
88
10.2.4 Assembly Wrap-up
10.2.4 Assembly Wrap-up
89
10.2.5 Models of Computation
10.2.5 Models of Computation
90
10.2.6 Computability, Universality
10.2.6 Computability, Universality
91
10.2.7 Uncomputable Functions
10.2.7 Uncomputable Functions
92
10.2.8 Worked Examples: Beta Assembly
10.2.8 Worked Examples: Beta Assembly
93
11.2.1 Iterpretation and Compilation
11.2.1 Iterpretation and Compilation
94
11.2.2 Compiling Expressions
11.2.2 Compiling Expressions
95
11.2.3 Compiling Statements
11.2.3 Compiling Statements
96
11.2.4 Compiler Frontend
11.2.4 Compiler Frontend
97
11.2.5 Optimization and Code Generation
11.2.5 Optimization and Code Generation
98
11.2.6 Worked Examples
11.2.6 Worked Examples
99
12.2.1 Procedures
12.2.1 Procedures
100
12.2.2 Activation Records and Stacks
12.2.2 Activation Records and Stacks
101
12.2.3 Stack Frame Organization
12.2.3 Stack Frame Organization
102
12.2.4 Compiling a Procedure
12.2.4 Compiling a Procedure
103
12.2.5 Stack Detective
12.2.5 Stack Detective
104
12.2.6 Worked Examples: Procedures and Stacks
12.2.6 Worked Examples: Procedures and Stacks
105
13.2.1 Building Blocks
13.2.1 Building Blocks
106
13.2.2 ALU Instructions
13.2.2 ALU Instructions
107
13.2.3 Load and Store
13.2.3 Load and Store
108
13.2.4 Jumps and Branches
13.2.4 Jumps and Branches
109
13.2.5 Exceptions
13.2.5 Exceptions
110
13.2.6 Summary
13.2.6 Summary
111
13.2.7 Worked Examples: A Better Beta
13.2.7 Worked Examples: A Better Beta
112
13.2.7 Worked Examples: Beta Control Signals
13.2.7 Worked Examples: Beta Control Signals
113
14.2.1 Memory Technologies
14.2.1 Memory Technologies
114
14.2.2 SRAM
14.2.2 SRAM
115
14.2.3 DRAM
14.2.3 DRAM
116
14.2.4 Non-volatile Storage; Using the Hierarchy
14.2.4 Non-volatile Storage; Using the Hierarchy
117
14.2.5 The Locality Principle
14.2.5 The Locality Principle
118
14.2.6 Caches
14.2.6 Caches
119
14.2.7 Direct-mapped Caches
14.2.7 Direct-mapped Caches
120
14.2.8 Block Size; Cache Conflicts
14.2.8 Block Size; Cache Conflicts
121
14.2.9 Associative Caches
14.2.9 Associative Caches
122
14.2.10 Write Strategies
14.2.10 Write Strategies
123
14.2.11 Worked Examples: Cache Benefits
14.2.11 Worked Examples: Cache Benefits
124
14.2.11 Worked Examples: Caches
14.2.11 Worked Examples: Caches
125
15.2.1 Improving Beta Performance
15.2.1 Improving Beta Performance
126
15.2.2 Basic 5-Stage Pipeline
15.2.2 Basic 5-Stage Pipeline
127
15.2.3 Data Hazards
15.2.3 Data Hazards
128
15.2.4 Control Hazards
15.2.4 Control Hazards
129
15.2.5 Exceptions and Interrupts
15.2.5 Exceptions and Interrupts
130
15.2.6 Pipelining Summary
15.2.6 Pipelining Summary
131
15.2.7 Worked Examples: Pipelined Beta
15.2.7 Worked Examples: Pipelined Beta
132
15.2.7 Worked Examples: Beta Junkyard
15.2.7 Worked Examples: Beta Junkyard
133
16.2.1 Even More Memory Hierarchy
16.2.1 Even More Memory Hierarchy
134
16.2.2 Basics of Virtual Memory
16.2.2 Basics of Virtual Memory
135
16.2.3 Page Faults
16.2.3 Page Faults
136
16.2.4 Building the MMU
16.2.4 Building the MMU
137
16.2.5 Contexts
16.2.5 Contexts
138
16.2.6 MMU Improvements
16.2.6 MMU Improvements
139
16.2.7 Worked Examples: Virtual Memory
16.2.7 Worked Examples: Virtual Memory
140
17.2.1 Recap: Virtual Memory
17.2.1 Recap: Virtual Memory
141
17.2.2 Processes
17.2.2 Processes
142
17.2.3 Timesharing
17.2.3 Timesharing
143
17.2.4 Handling Illegal Instructions
17.2.4 Handling Illegal Instructions
144
17.2.5 Supevisor Calls
17.2.5 Supevisor Calls
145
17.2.6 Worked Examples: Operating Systems
17.2.6 Worked Examples: Operating Systems
146
18.2.1 OS Device Handlers
18.2.1 OS Device Handlers
147
18.2.2 SVCs for Input/Output
18.2.2 SVCs for Input/Output
148
18.2.3 Example: Match Handler with OS
18.2.3 Example: Match Handler with OS
149
18.2.4 Real Time
18.2.4 Real Time
150
18.2.5 Weak Priorities
18.2.5 Weak Priorities
151
18.2.6 Strong Priorities
18.2.6 Strong Priorities
152
18.2.7 Example: Priorities in Action!
18.2.7 Example: Priorities in Action!
153
18.2.8 Worked Examples: Devices and Interrupts
18.2.8 Worked Examples: Devices and Interrupts
154
19.2.1 Interprocess Communication
19.2.1 Interprocess Communication
155
19.2.2 Semaphores
19.2.2 Semaphores
156
19.2.3 Atomic Transactions
19.2.3 Atomic Transactions
157
19.2.4 Semaphore Implementation
19.2.4 Semaphore Implementation
158
19.2.5 Deadlock
19.2.5 Deadlock
159
19.2.6 Worked Examples: Semaphores
19.2.6 Worked Examples: Semaphores
160
20.2.1 System-level Interfaces
20.2.1 System-level Interfaces
161
20.2.2 Wires
20.2.2 Wires
162
20.2.3 Buses
20.2.3 Buses
163
20.2.4 Point-to-point Communication
20.2.4 Point-to-point Communication
164
20.2.5 System-level Interconnect
20.2.5 System-level Interconnect
165
20.2.6 Communication Topologies
20.2.6 Communication Topologies
166
21.2.1 Instruction-level Parallelism
21.2.1 Instruction-level Parallelism
167
21.2.2 Data-level Parallelism
21.2.2 Data-level Parallelism
168
21.2.3 Thread-level Parallelism
21.2.3 Thread-level Parallelism
169
21.2.4 Shared Memory & Caches
21.2.4 Shared Memory & Caches
170
21.2.5 Cache Coherence
21.2.5 Cache Coherence
171
21.2.6 6.004 Wrap-up
21.2.6 6.004 Wrap-up
172
An Interview with Christopher Terman on Teaching Computation Structures
An Interview with Christopher Terman on Teaching Computation Structures